Board test coverage

Which boards in TF CI were seen testing which firmware branch, and with what result. Test results for the last 30 days; older history is at job level only.

Data as of 29 Oct 2026, 09:00 UTCLast synced:LAVA 29 Oct 2026, 09:00 UTCJenkins 29 Oct 2026, 09:01 UTCS3 export 7 Oct 2026, 09:53 UTC

TF-A

Scroll the matrix sideways to see every branch.
TF-A boards by branch and suite, last 30 days, branch and nightly.
Board and suitemasterLTS 2.14LTS 2.12LTS 2.10LTS 2.8integrationUnattributed
Arm
Juno22 observed devices, Boot, 14.5 checks
Linux boot99%496n=496 with verdict100%297n=297 with verdict100%320n=320 with verdict100%322n=322 with verdict100%320n=320 with verdict1/11n=1 with verdictdeclared until Oct 2026
Linux shutdown100%84n=84 with verdict100%50n=50 with verdict100%54n=54 with verdict100%54n=54 with verdict100%54n=54 with verdictdeclared until Oct 2026declared until Oct 2026
TFTF (Trusted Firmware Test Framework)100%958n=958 with verdict100%600n=600 with verdict99%634n=634 with verdict100%637n=633 with verdict100%637n=634 with verdictdeclared until Oct 2026declared until Oct 2026
TFTF run checks100%161n=161 with verdict100%100n=100 with verdict100%107n=107 with verdict100%108n=108 with verdict100%107n=107 with verdictdeclared until Oct 2026declared until Oct 2026
N1SDP2 observed devices, Boot
TF-A boot to UEFI100%41n=41 with verdict100%25n=25 with verdict100%27n=27 with verdict100%27n=27 with verdict100%27n=27 with verdictdeclared until Oct 2026declared until Oct 2026
TFTF (Trusted Firmware Test Framework)100%51n=51 with verdict100%25n=25 with verdict100%26n=26 with verdictno verdict1n=0 with verdict··declared until Oct 2026
Chromebook
Asurada (MT8192)3 observed devices, Boot
BL31 boot to depthcharge100%41n=41 with verdict100%25n=25 with verdict100%27n=27 with verdict100%27n=27 with verdict100%27n=27 with verdictdeclared until Oct 2026declared until Oct 2026
Cherry (MT8195)3 observed devices, Boot
BL31 boot to depthcharge100%41n=41 with verdict100%25n=25 with verdict100%27n=27 with verdict100%27n=27 with verdict1/11n=1 with verdictdeclared until Oct 2026declared until Oct 2026
Corsola (MT8186)3 observed devices, Boot
BL31 boot to depthcharge100%40n=40 with verdict100%25n=25 with verdict100%27n=27 with verdict100%27n=27 with verdict1/11n=1 with verdictdeclared until Oct 2026declared until Oct 2026
Geralt (MT8188)3 observed devices, Boot
BL31 boot to depthcharge100%40n=40 with verdict100%25n=25 with verdict100%27n=27 with verdict100%27n=27 with verdict1/11n=1 with verdictdeclared until Oct 2026declared until Oct 2026
Rauru (MT8196)4 observed devices, Boot
BL31 boot to depthcharge100%40n=40 with verdict100%25n=25 with verdict···declared until Oct 2026declared until Oct 2026
Trogdor (SC7180)4 observed devices, Boot
BL31 boot to depthcharge100%43n=41 with verdict100%26n=26 with verdict96%27n=27 with verdict100%27n=27 with verdict1/11n=1 with verdict2/22n=2 with verdictdeclared until Oct 2026
Raspberry Pi
RPi (BCM2837)2 observed devices, Boot
TF-A boot to Linux100%80n=80 with verdict····declared until Oct 2026declared until Oct 2026
STMicroelectronics
STM32MP15X-Eval3 observed devices, Boot
SP_min boot to Linux100%40n=40 with verdict100%25n=25 with verdict100%26n=26 with verdict100%27n=27 with verdict·declared until Oct 2026declared until Oct 2026

TF-M

Scroll the matrix sideways to see every branch.
TF-M boards by branch and suite, last 30 days, branch and nightly.
Board and suitemainreleaseUnattributed
Arm
Musca-B9 observed devices, 107.4 assertions
Non-secure bootdeclared until Oct 2026·declared until Sep 2026
MCUboot integration100%150n=150 with verdict·declared until Oct 2026
Non-secure regression100%150n=150 with verdict·declared until Oct 2026
PSA API compliance··declared until Aug 2026
Secure regression100%150n=150 with verdict·declared until Oct 2026
NXP
FRDMMCXN9473 observed devices, 156.0 assertions
Non-secure regression100%30n=30 with verdict·declared until Oct 2026
Secure regression100%30n=30 with verdict·declared until Oct 2026
LPCXpresso55S693 observed devices, 139.1 assertions
Non-secure bootdeclared until Oct 2026·declared until Sep 2026
Non-secure regression100%30n=30 with verdict·declared until Oct 2026
Secure regression100%30n=30 with verdict·declared until Oct 2026
STMicroelectronics
B-U585I-IOT02A3 observed devices, 194.6 assertions
Non-secure regression100%70n=70 with verdict·declared until Oct 2026
Secure regression100%70n=70 with verdict·declared until Oct 2026
STM32H573I-DK3 observed devices, 194.6 assertions
Non-secure regression100%70n=70 with verdict·declared until Oct 2026
Secure regression100%70n=70 with verdict·declared until Oct 2026
STM32U3C5ZI-Q3 observed devices, 198.0 assertions
Non-secure regression2/22n=2 with verdict··
Secure regression2/22n=2 with verdict··
STM32WBA65I-DK14 observed devices, 197.0 assertions
Non-secure regression100%68n=68 with verdict·declared until Oct 2026
Secure regression100%68n=68 with verdict·declared until Oct 2026
Other boards
Nucleo-U3C5ZI-Q3 observed devices, 196.2 assertions
Non-secure regression100%10n=10 with verdict··
Secure regression100%10n=10 with verdict··

How to read the matrix

  • Pass
  • Code: a test failed, or the job failed after boot
  • Lab: the run did not complete for lab reasons
  • Cancelled
  • Unclassified: the cause was not recorded
  • Declared in job definitions, not observed in this window. Declared never means passed.
  • No observation: we did not see this run, which is not the same as unsupported
  • Last 10 evaluations, oldest on the left. Short means pass, tall means a problem; hatched is the lab, solid is the code; a capped short tick passed on retry.
Rate is evaluations that passed after retries, out of evaluations that passed or failed in the code. With fewer than 5 of those it is shown as a fraction. The base n counts pass and code verdicts. The count beside the rate includes all evaluations, including lab, cancelled and unclassified.
Not shown here: FVP and QEMU testing, which runs in TuxSuite, and Allow-CI +1 runs, which are build-only and never reach a board. Their absence from this page is not a coverage gap.

12 months of CI attempts

Job level: attempts per month and how many completed. Test-case detail exists only for the live window. Months without data are drawn as gaps, never as zero.

TF-A

  • CI attempts per month
  • Complete attempts, %
Test-case detail: September 2026 to October 2026.
Month
Complete
Incomplete
Cancelled
Completion
Days covered
Nov 2025
4969
179
0
96.5% of 5148
30 of 30
Dec 2025
5447
120
0
97.8% of 5567
31 of 31
Jan 2026
5785
297
1
95.1% of 6082
31 of 31
Feb 2026
4922
1313
0
78.9% of 6235
27 of 28
Mar 2026
8463
214
22
97.5% of 8677
31 of 31
Apr 2026
12865
635
1769
95.3% of 13500
30 of 30
May 2026
11562
615
87
94.9% of 12177
31 of 31
Jun 2026
13585
424
387
97.0% of 14009
30 of 30
Jul 2026
16045
147
844
99.1% of 16192
31 of 31
Aug 2026
11587
86
172
99.3% of 11673
31 of 31
Sep 2026
14787
107
155
99.3% of 14894
30 of 30
Oct 2026
13197
201
114
98.5% of 13398
29 of 29

TF-M

  • CI attempts per month
  • Complete attempts, %
Test-case detail: September 2026 to October 2026.
Month
Complete
Incomplete
Cancelled
Completion
Days covered
Nov 2025
10044
111
1
98.9% of 10155
30 of 30
Dec 2025
9044
261
10
97.2% of 9305
31 of 31
Jan 2026
6802
152
706
97.8% of 6954
31 of 31
Feb 2026
3712
2249
213
62.3% of 5961
27 of 28
Mar 2026
7062
159
220
97.8% of 7221
31 of 31
Apr 2026
10240
543
372
95.0% of 10783
30 of 30
May 2026
4481
7
63
99.8% of 4488
31 of 31
Jun 2026
3213
11
119
99.7% of 3224
30 of 30
Jul 2026
1238
167
1
88.1% of 1405
31 of 31
Aug 2026
1566
183
0
89.5% of 1749
31 of 31
Sep 2026
932
147
0
86.4% of 1079
30 of 30
Oct 2026
800
5
0
99.4% of 805
29 of 29
Job level only: 1 Oct 2025 to 27 Feb 2026No data held: 28 Feb 2026 to 28 Feb 2026Job level only: 1 Mar 2026 to 6 Sep 2026Test-case detail: 7 Sep 2026 to 30 Sep 2026Test-case detail: 1 Oct 2026 to 29 Oct 2026
Job-level history: 1 Oct 2025 to 6 Sep 2026. Test-case detail: 7 Sep 2026 to 29 Oct 2026. 1 day without data.