Board test coverage

Which boards in TF CI were seen testing which firmware branch, and with what result. Test results for the last 30 days; older history is at job level only.

Data as of 28 Oct 2026, 13:02 UTCLast synced:LAVA 28 Oct 2026, 13:02 UTCJenkins 28 Oct 2026, 13:03 UTCS3 export 7 Oct 2026, 09:53 UTC

TF-A

Scroll the matrix sideways to see every branch.
TF-A boards by branch and suite, last 30 days, all ci runs.
Board and suitemasterLTS 2.14LTS 2.12LTS 2.10LTS 2.8integrationUnattributed
Arm
Juno22 observed devices, Boot, 14.4 checks
Linux boot99%484n=484 with verdict100%525n=525 with verdict100%392n=392 with verdict100%442n=442 with verdict100%560n=560 with verdict100%1,103n=1,103 with verdict100%72n=72 with verdict
Linux shutdown100%82n=82 with verdict100%88n=88 with verdict100%66n=66 with verdict100%74n=74 with verdict100%94n=94 with verdict100%184n=184 with verdict100%12n=12 with verdict
TFTF (Trusted Firmware Test Framework)100%932n=932 with verdict100%994n=994 with verdict99%774n=774 with verdict100%857n=853 with verdict100%1,049n=1,046 with verdict100%1,828n=1,828 with verdict100%150n=150 with verdict
TFTF run checks100%157n=157 with verdict100%173n=173 with verdict100%131n=131 with verdict100%148n=148 with verdict100%187n=187 with verdict100%363n=363 with verdict100%24n=24 with verdict
N1SDP2 observed devices, Boot
TF-A boot to UEFI100%40n=40 with verdict100%44n=44 with verdict100%33n=33 with verdict100%37n=37 with verdict100%47n=47 with verdict100%94n=94 with verdict100%6n=6 with verdict
TFTF (Trusted Firmware Test Framework)100%49n=49 with verdict100%30n=30 with verdict100%31n=31 with verdictno verdict1n=0 with verdict··100%10n=10 with verdict
Chromebook
Asurada (MT8192)3 observed devices, Boot
BL31 boot to depthcharge100%40n=40 with verdict100%45n=45 with verdict100%33n=33 with verdict100%37n=37 with verdict100%47n=47 with verdict100%94n=94 with verdict100%6n=6 with verdict
Cherry (MT8195)3 observed devices, Boot
BL31 boot to depthcharge100%40n=40 with verdict100%44n=44 with verdict100%33n=33 with verdict100%37n=37 with verdict1/11n=1 with verdict100%95n=95 with verdict100%6n=6 with verdict
Corsola (MT8186)3 observed devices, Boot
BL31 boot to depthcharge100%39n=39 with verdict100%44n=44 with verdict100%33n=33 with verdict100%37n=37 with verdict1/11n=1 with verdict100%95n=95 with verdict100%6n=6 with verdict
Geralt (MT8188)3 observed devices, Boot
BL31 boot to depthcharge100%39n=39 with verdict100%45n=45 with verdict100%32n=32 with verdict100%36n=36 with verdict1/11n=1 with verdict100%88n=88 with verdict100%5n=5 with verdict
Rauru (MT8196)4 observed devices, Boot
BL31 boot to depthcharge100%39n=39 with verdict100%44n=44 with verdict···100%93n=93 with verdict100%5n=5 with verdict
Trogdor (SC7180)4 observed devices, Boot
BL31 boot to depthcharge100%42n=40 with verdict100%46n=45 with verdict96%33n=33 with verdict100%37n=37 with verdict1/11n=1 with verdict98%96n=96 with verdict100%6n=6 with verdict
Raspberry Pi
RPi (BCM2837)2 observed devices, Boot
TF-A boot to Linux100%78n=78 with verdict····100%189n=189 with verdict100%12n=12 with verdict
STMicroelectronics
STM32MP15X-Eval3 observed devices, Boot
SP_min boot to Linux100%39n=39 with verdict100%44n=44 with verdict100%32n=32 with verdict100%37n=37 with verdict·100%95n=95 with verdict100%6n=6 with verdict

TF-M

Scroll the matrix sideways to see every branch.
TF-M boards by branch and suite, last 30 days, all ci runs.
Board and suitemainreleaseUnattributed
Arm
Musca-B9 observed devices, 107.4 assertions
Non-secure bootdeclared until Oct 2026·declared until Sep 2026
MCUboot integration100%145n=145 with verdict·100%20n=20 with verdict
Non-secure regression100%145n=145 with verdict·100%20n=20 with verdict
PSA API compliance··declared until Aug 2026
Secure regression100%145n=145 with verdict·100%20n=20 with verdict
NXP
FRDMMCXN9473 observed devices, 156.0 assertions
Non-secure regression100%29n=29 with verdict·4/44n=4 with verdict
Secure regression100%29n=29 with verdict·4/44n=4 with verdict
LPCXpresso55S693 observed devices, 139.1 assertions
Non-secure bootdeclared until Oct 2026·declared until Sep 2026
Non-secure regression100%29n=29 with verdict·4/44n=4 with verdict
Secure regression100%29n=29 with verdict·4/44n=4 with verdict
STMicroelectronics
B-U585I-IOT02A3 observed devices, 194.6 assertions
Non-secure regression100%206n=206 with verdict·100%38n=38 with verdict
Secure regression100%206n=206 with verdict·100%38n=38 with verdict
STM32H573I-DK3 observed devices, 194.6 assertions
Non-secure regression100%206n=206 with verdict·100%38n=38 with verdict
Secure regression100%206n=206 with verdict·100%38n=38 with verdict
STM32U3C5ZI-Q3 observed devices, 198.0 assertions
Non-secure regression2/22n=2 with verdict··
Secure regression2/22n=2 with verdict··
STM32WBA65I-DK14 observed devices, 197.0 assertions
Non-secure regression100%66n=66 with verdict·100%8n=8 with verdict
Secure regression100%66n=66 with verdict·100%8n=8 with verdict
Other boards
Nucleo-U3C5ZI-Q3 observed devices, 195.8 assertions
Non-secure regression100%8n=8 with verdict··
Secure regression100%8n=8 with verdict··

How to read the matrix

  • Pass
  • Code: a test failed, or the job failed after boot
  • Lab: the run did not complete for lab reasons
  • Cancelled
  • Unclassified: the cause was not recorded
  • Declared in job definitions, not observed in this window. Declared never means passed.
  • No observation: we did not see this run, which is not the same as unsupported
  • Last 10 evaluations, oldest on the left. Short means pass, tall means a problem; hatched is the lab, solid is the code; a capped short tick passed on retry.
Rate is evaluations that passed after retries, out of evaluations that passed or failed in the code. With fewer than 5 of those it is shown as a fraction. The base n counts pass and code verdicts. The count beside the rate includes all evaluations, including lab, cancelled and unclassified.
Not shown here: FVP and QEMU testing, which runs in TuxSuite, and Allow-CI +1 runs, which are build-only and never reach a board. Their absence from this page is not a coverage gap.

12 months of CI attempts

Job level: attempts per month and how many completed. Test-case detail exists only for the live window. Months without data are drawn as gaps, never as zero.

TF-A

  • CI attempts per month
  • Complete attempts, %
Test-case detail: September 2026 to October 2026.
Month
Complete
Incomplete
Cancelled
Completion
Days covered
Nov 2025
4969
179
0
96.5% of 5148
30 of 30
Dec 2025
5447
120
0
97.8% of 5567
31 of 31
Jan 2026
5785
297
1
95.1% of 6082
31 of 31
Feb 2026
4922
1313
0
78.9% of 6235
27 of 28
Mar 2026
8463
214
22
97.5% of 8677
31 of 31
Apr 2026
12865
635
1769
95.3% of 13500
30 of 30
May 2026
11562
615
87
94.9% of 12177
31 of 31
Jun 2026
13585
424
387
97.0% of 14009
30 of 30
Jul 2026
16045
147
844
99.1% of 16192
31 of 31
Aug 2026
11587
86
172
99.3% of 11673
31 of 31
Sep 2026
14787
107
155
99.3% of 14894
30 of 30
Oct 2026
12820
201
114
98.5% of 13021
28 of 28

TF-M

  • CI attempts per month
  • Complete attempts, %
Test-case detail: September 2026 to October 2026.
Month
Complete
Incomplete
Cancelled
Completion
Days covered
Nov 2025
10044
111
1
98.9% of 10155
30 of 30
Dec 2025
9044
261
10
97.2% of 9305
31 of 31
Jan 2026
6802
152
706
97.8% of 6954
31 of 31
Feb 2026
3712
2249
213
62.3% of 5961
27 of 28
Mar 2026
7062
159
220
97.8% of 7221
31 of 31
Apr 2026
10240
543
372
95.0% of 10783
30 of 30
May 2026
4481
7
63
99.8% of 4488
31 of 31
Jun 2026
3213
11
119
99.7% of 3224
30 of 30
Jul 2026
1238
167
1
88.1% of 1405
31 of 31
Aug 2026
1566
183
0
89.5% of 1749
31 of 31
Sep 2026
932
147
0
86.4% of 1079
30 of 30
Oct 2026
777
5
0
99.4% of 782
28 of 28
Job level only: 1 Oct 2025 to 27 Feb 2026No data held: 28 Feb 2026 to 28 Feb 2026Job level only: 1 Mar 2026 to 6 Sep 2026Test-case detail: 7 Sep 2026 to 30 Sep 2026Test-case detail: 1 Oct 2026 to 28 Oct 2026
Job-level history: 1 Oct 2025 to 6 Sep 2026. Test-case detail: 7 Sep 2026 to 28 Oct 2026. 1 day without data.