STM32U3C5ZI-Q
- Status
- New3 units live.
- SoC and family
- STM32U3C5ZI, STMicroelectronics
- Device type
stm32u3c5zi-q- Activity
- First seen 10 Sep 2026, last seen 16 Oct 2026.
Data as of 28 Oct 2026, 18:19 UTCLast synced:LAVA 28 Oct 2026, 18:19 UTCJenkins 28 Oct 2026, 18:32 UTCS3 export 7 Oct 2026, 09:53 UTC
Evaluations
22 attempts, 0 cancelledCompletion
100.0%of 2 attemptsComplete out of complete and incomplete attempts. Cancelled attempts are listed, never counted.Evaluated pass rate
100.0%of 2 evaluations with a verdictFinal attempts that passed, out of pass and code. Lab 0, cancelled 0 and unclassified 0 are shown, never folded in.Failed after retries
0 of 20 failed first time, 0 passed on retryChanges with a failed boot on this board
0 of 0Allow-CI+2 for TF-A; linked TF-M runs. 0 with no boot verdict. Linked to a change: 0.0% of 2 evaluationsLast 30 days
Evaluations per day, stacked by final outcome.
Pass
Passed on retry
Lab
Code
Cancelled
Unclassified
History by month
Before the live window we know whether each attempt completed and how retries ended, not why it failed or which change it was. Months with no data held are listed under the chart.
- Evaluations per month
- Incomplete attempts, % of attempts
- Failed after retries, % of evaluations
Incidents marked: Lab 17 Sep.
Test-case detail: September 2026 to October 2026.
Units
CI attempts per physical unit, retries included. Passing on another unit can help identify a unit fault. Health checks are fleet health.
Evaluations
One row per builder build on this board, newest first, with every attempt. CI runs only; 2 of 2 shown.
Fleet health
Health checks, not CI results. They never count towards any rate on this page.
No health check ran on this board in the last 7 days.
Incidents
- Lab 17 Sep 2026 to 18 Sep 2026
LAVA logger DNS failures