Board test coverage
Which boards in TF CI were seen testing which firmware branch, and with what result. Test results for the last 7 days; older history is at job level only.
Data as of 29 Oct 2026, 18:19 UTCLast synced:LAVA 29 Oct 2026, 18:19 UTCJenkins 29 Oct 2026, 18:22 UTCS3 export 7 Oct 2026, 09:53 UTC
Window
Runs
Names
Project
TF-A
TF-A boards by branch and suite, last 7 days, branch and nightly.
master | LTS 2.14 | LTS 2.12 | LTS 2.10 | LTS 2.8 | integration | Unattributed | |
|---|---|---|---|---|---|---|---|
Arm | |||||||
Juno22 observed devices, Boot, 14.0 checks | |||||||
Linux boot | |||||||
Linux shutdown | |||||||
TFTF (Trusted Firmware Test Framework) | |||||||
TFTF run checks | |||||||
N1SDP2 observed devices, Boot | |||||||
TF-A boot to UEFI | |||||||
TFTF (Trusted Firmware Test Framework) | · | · | |||||
Chromebook | |||||||
Asurada (MT8192)3 observed devices, Boot | |||||||
BL31 boot to depthcharge | |||||||
Cherry (MT8195)3 observed devices, Boot | |||||||
BL31 boot to depthcharge | |||||||
Corsola (MT8186)3 observed devices, Boot | |||||||
BL31 boot to depthcharge | |||||||
Geralt (MT8188)3 observed devices, Boot | |||||||
BL31 boot to depthcharge | |||||||
Rauru (MT8196)4 observed devices, Boot | |||||||
BL31 boot to depthcharge | · | · | · | ||||
Trogdor (SC7180)4 observed devices, Boot | |||||||
BL31 boot to depthcharge | |||||||
Raspberry Pi | |||||||
RPi (BCM2837)2 observed devices, Boot | |||||||
TF-A boot to Linux | · | · | · | · | |||
STMicroelectronics | |||||||
STM32MP15X-Eval3 observed devices, Boot | |||||||
SP_min boot to Linux | · |
TF-M
TF-M boards by branch and suite, last 7 days, branch and nightly.
main | release | Unattributed | |
|---|---|---|---|
Arm | |||
Musca-B9 observed devices, 105.7 assertions | |||
Non-secure boot | · | ||
MCUboot integration | · | ||
Non-secure regression | · | ||
PSA API compliance | · | · | |
Secure regression | · | ||
NXP | |||
FRDMMCXN9473 observed devices, 156.0 assertions | |||
Non-secure regression | · | ||
Secure regression | · | ||
LPCXpresso55S693 observed devices, 136.5 assertions | |||
Non-secure boot | · | ||
Non-secure regression | · | ||
Secure regression | · | ||
STMicroelectronics | |||
B-U585I-IOT02A3 observed devices, 194.5 assertions | |||
Non-secure regression | · | ||
Secure regression | · | ||
STM32H573I-DK3 observed devices, 194.5 assertions | |||
Non-secure regression | · | ||
Secure regression | · | ||
STM32U3C5ZI-Q3 observed devices | |||
Non-secure regression | · | · | |
Secure regression | · | · | |
STM32WBA65I-DK14 observed devices, 196.9 assertions | |||
Non-secure regression | · | ||
Secure regression | · | ||
Other boards | |||
Nucleo-U3C5ZI-Q3 observed devices, 198.0 assertions | |||
Non-secure regression | · | · | |
Secure regression | · | · |
How to read the matrix
- Pass
- Code: a test failed, or the job failed after boot
- Lab: the run did not complete for lab reasons
- Cancelled
- Unclassified: the cause was not recorded
- Declared in job definitions, not observed in this window. Declared never means passed.
- No observation: we did not see this run, which is not the same as unsupported
- Last 10 evaluations, oldest on the left. Short means pass, tall means a problem; hatched is the lab, solid is the code; a capped short tick passed on retry.
Rate is evaluations that passed after retries, out of evaluations that passed or failed in the code. With fewer than 5 of those it is shown as a fraction. The base n counts pass and code verdicts. The count beside the rate includes all evaluations, including lab, cancelled and unclassified.
Not shown here: FVP and QEMU testing, which runs in TuxSuite, and Allow-CI +1 runs, which are build-only and never reach a board. Their absence from this page is not a coverage gap.
12 months of CI attempts
Job level: attempts per month and how many completed. Test-case detail exists only for the live window. Months without data are drawn as gaps, never as zero.
TF-A
- CI attempts per month
- Complete attempts, %
Test-case detail: September 2026 to October 2026.
TF-M
- CI attempts per month
- Complete attempts, %
Test-case detail: September 2026 to October 2026.