Board test coverage

Which boards in TF CI were seen testing which firmware branch, and with what result. Test results for the last 7 days; older history is at job level only.

Data as of 29 Oct 2026, 18:19 UTCLast synced:LAVA 29 Oct 2026, 18:19 UTCJenkins 29 Oct 2026, 18:22 UTCS3 export 7 Oct 2026, 09:53 UTC

TF-A

TF-A boards by branch and suite, last 7 days, all ci runs.

Board and suite
master
LTS 2.14
LTS 2.12
LTS 2.10
LTS 2.8
integration
Unattributed
Arm
juno22 observed devices, Boot, 14.0 checks
lava
0_shutdown, shutdown
TFTF, tftf
0_tftf-boot-banner, 0_tftf-exit, 0_tftf-mem-protect-case, 0_tftf-mem-protect-sentinel, 0_tftf-power-cycle-0, 0_tftf-power-cycle-1, 0_tftf-resume-after-mem-protect, 0_tftf-resume-after-warm-reset, 0_tftf-tests-crashed-zero, 0_tftf-tests-failed-zero, 0_tftf-tests-passed, 0_tftf-warm-reset-case, 0_tftf-warm-reset-sentinel-modified, tftf-boot-banner, tftf-exit, tftf-mem-protect-case, tftf-mem-protect-sentinel, tftf-power-cycle-0, tftf-power-cycle-1, tftf-resume-after-mem-protect, tftf-resume-after-warm-reset, tftf-tests-crashed-zero, tftf-tests-failed-zero, tftf-tests-passed, tftf-warm-reset-case, tftf-warm-reset-sentinel-modified
n1sdp2 observed devices, Boot
int_1, lava
TFTF, tftf
Β·
Β·
Chromebook
mt8192-asurada-rev13 observed devices, Boot
int_1, int_2, lava
mt8195-cherry-tomato-r23 observed devices, Boot
int_1, int_2, lava
mt8186-corsola-tentacruel3 observed devices, Boot
int_1, int_2, lava
mt8188-geralt3 observed devices, Boot
int_1, int_2, lava
mt8196-rauru-navi4 observed devices, Boot
int_1, int_2, lava
Β·
Β·
Β·
sc7180-trogdor-lazor-limozeen4 observed devices, Boot
int_1, int_2, lava
Raspberry Pi
bcm2837-rpi-3-b-322 observed devices, Boot
int_1, lava
Β·
Β·
Β·
Β·
STMicroelectronics
stm32mp15x-eval3 observed devices, Boot
int_1, lava
Β·

TF-M

TF-M boards by branch and suite, last 7 days, all ci runs.

Board and suite
main
release
Unattributed
Arm
musca-b9 observed devices, 105.7 assertions
NS_SYSTEM_BOOTING
Β·
mcuboot_suite
Β·
non_secure_regression_suite
Β·
psa_api_suite
Β·
Β·
secure_regression_suite
Β·
NXP
frdmmcxn9473 observed devices, 156.0 assertions
non_secure_regression_suite
Β·
secure_regression_suite
Β·
lpcxpresso55s693 observed devices, 136.5 assertions
NS_SYSTEM_BOOTING
Β·
non_secure_regression_suite
Β·
secure_regression_suite
Β·
STMicroelectronics
b-u585i-iot02a3 observed devices, 194.5 assertions
non_secure_regression_suite
Β·
secure_regression_suite
Β·
stm32h573i-dk3 observed devices, 194.5 assertions
non_secure_regression_suite
Β·
secure_regression_suite
Β·
stm32u3c5zi-q3 observed devices
non_secure_regression_suite
Β·
Β·
secure_regression_suite
Β·
Β·
stm32wba65i-dk14 observed devices, 196.9 assertions
non_secure_regression_suite
Β·
secure_regression_suite
Β·
Other boards
nucleo-u3c5zi-q3 observed devices, 198.0 assertions
non_secure_regression_suite
Β·
Β·
secure_regression_suite
Β·
Β·

How to read the matrix

  • Pass
  • Code: a test failed, or the job failed after boot
  • Lab: the run did not complete for lab reasons
  • Cancelled
  • Unclassified: the cause was not recorded
  • Declared in job definitions, not observed in this window. Declared never means passed.
  • No observation: we did not see this run, which is not the same as unsupported
  • Last 10 evaluations, oldest on the left. Short means pass, tall means a problem; hatched is the lab, solid is the code; a capped short tick passed on retry.
Rate is evaluations that passed after retries, out of evaluations that passed or failed in the code. With fewer than 5 of those it is shown as a fraction. The base n counts pass and code verdicts. The count beside the rate includes all evaluations, including lab, cancelled and unclassified.
Not shown here: FVP and QEMU testing, which runs in TuxSuite, and Allow-CI +1 runs, which are build-only and never reach a board. Their absence from this page is not a coverage gap.

12 months of CI attempts

Job level: attempts per month and how many completed. Test-case detail exists only for the live window. Months without data are drawn as gaps, never as zero.

TF-A

  • CI attempts per month
  • Complete attempts, %
Test-case detail: September 2026 to October 2026.
Month
Complete
Incomplete
Cancelled
Completion
Days covered
Nov 2025
4969
179
0
96.5% of 5148
30 of 30
Dec 2025
5447
120
0
97.8% of 5567
31 of 31
Jan 2026
5785
297
1
95.1% of 6082
31 of 31
Feb 2026
4922
1313
0
78.9% of 6235
27 of 28
Mar 2026
8463
214
22
97.5% of 8677
31 of 31
Apr 2026
12865
635
1769
95.3% of 13500
30 of 30
May 2026
11562
615
87
94.9% of 12177
31 of 31
Jun 2026
13585
424
387
97.0% of 14009
30 of 30
Jul 2026
16045
147
844
99.1% of 16192
31 of 31
Aug 2026
11587
86
172
99.3% of 11673
31 of 31
Sep 2026
14787
107
155
99.3% of 14894
30 of 30
Oct 2026
13537
202
114
98.5% of 13739
29 of 29

TF-M

  • CI attempts per month
  • Complete attempts, %
Test-case detail: September 2026 to October 2026.
Month
Complete
Incomplete
Cancelled
Completion
Days covered
Nov 2025
10044
111
1
98.9% of 10155
30 of 30
Dec 2025
9044
261
10
97.2% of 9305
31 of 31
Jan 2026
6802
152
706
97.8% of 6954
31 of 31
Feb 2026
3712
2249
213
62.3% of 5961
27 of 28
Mar 2026
7062
159
220
97.8% of 7221
31 of 31
Apr 2026
10240
543
372
95.0% of 10783
30 of 30
May 2026
4481
7
63
99.8% of 4488
31 of 31
Jun 2026
3213
11
119
99.7% of 3224
30 of 30
Jul 2026
1238
167
1
88.1% of 1405
31 of 31
Aug 2026
1566
183
0
89.5% of 1749
31 of 31
Sep 2026
932
147
0
86.4% of 1079
30 of 30
Oct 2026
800
5
0
99.4% of 805
29 of 29
Job level only: 1 Oct 2025 to 27 Feb 2026No data held: 28 Feb 2026 to 28 Feb 2026Job level only: 1 Mar 2026 to 6 Sep 2026Test-case detail: 7 Sep 2026 to 30 Sep 2026Test-case detail: 1 Oct 2026 to 29 Oct 2026
Job-level history: 1 Oct 2025 to 6 Sep 2026. Test-case detail: 7 Sep 2026 to 29 Oct 2026. 1 day without data.