STM32MP15X-Eval

Status
Live
3 units live.
SoC and family
STM32MP15X, STMicroelectronics
Device type
stm32mp15x-eval
Activity
First seen 1 Oct 2025, last seen 29 Oct 2026.
Data as of 29 Oct 2026, 18:19 UTCLast synced:LAVA 29 Oct 2026, 18:19 UTCJenkins 29 Oct 2026, 18:22 UTCS3 export 7 Oct 2026, 09:53 UTC
Evaluations
259260 attempts, 0 cancelled
Completion
99.6%of 260 attemptsComplete out of complete and incomplete attempts. Cancelled attempts are listed, never counted.
Evaluated pass rate
100.0%of 259 evaluations with a verdictFinal attempts that passed, out of pass and code. Lab 0, cancelled 0 and unclassified 0 are shown, never folded in.
Failed after retries
0 of 2591 failed first time, 1 passed on retry
Changes with a failed boot on this board
0 of 109Allow-CI+2 for TF-A; linked TF-M runs. 0 with no boot verdict. Linked to a change: 47.1% of 259 evaluations

Last 30 days

Evaluations per day, stacked by final outcome.

Test-case detail: 30 Sep 2026 to 30 Sep 2026Test-case detail: 1 Oct 2026 to 29 Oct 2026
Test-case detail: 30 Sep 2026 to 29 Oct 2026. 0 days without data.

History by month

Before the live window we know whether each attempt completed and how retries ended, not why it failed or which change it was. Months with no data held are listed under the chart.

  • Evaluations per month
  • Incomplete attempts, % of attempts
  • Failed after retries, % of evaluations
Incidents marked: Lab 17 Sep.
Test-case detail: September 2026 to October 2026.
Job level only: 1 Oct 2025 to 27 Feb 2026No data held: 28 Feb 2026 to 28 Feb 2026Job level only: 1 Mar 2026 to 6 Sep 2026Test-case detail: 7 Sep 2026 to 30 Sep 2026Test-case detail: 1 Oct 2026 to 29 Oct 2026
Job-level history: 1 Oct 2025 to 6 Sep 2026. Test-case detail: 7 Sep 2026 to 29 Oct 2026. 1 day without data.

Units

CI attempts per physical unit, retries included. Passing on another unit can help identify a unit fault. Health checks are fleet health.

1 of 1 first-attempt failures were on stm32mp15x-eval-02; 1 of them passed on another unit.

Unit
Attempts
First-attempt failures
Passed on another unit
Passed on the same unit
Last health check
78
1
1
0
Complete 29 Oct 16:46
92
0
0
0
Complete 29 Oct 11:03
90
0
0
0
Complete 29 Oct 13:53

Evaluations

One row per builder build on this board, newest first, with every attempt. CI runs only; 50 of 259 shown.

When
Build
Change
Branch
Attempts
Verdict
12 Oct 22:30
not recorded
master
built integration
Pass
12 Oct 17:00
feat(stm32mp2): save a copy of STM32 header
integration
built refs/changes/12/55312/1
Pass
12 Oct 13:49
fix(fvp): remove GIC crash reporting
integration
built refs/changes/88/55188/3
Pass
12 Oct 13:33
fix(plat/qemu): make BDF mapping top inclusive
integration
built refs/changes/85/52685/4
Pass
12 Oct 13:11
not recorded
master
built integration
Pass
12 Oct 13:05
not recorded
master
built integration
Pass
12 Oct 11:32
not recorded
master
built integration
Pass
12 Oct 10:01
refactor(cpus): move C support files into the helpers directory
integration
built refs/changes/27/55227/1
Pass
12 Oct 07:24
not recorded
master
Pass
12 Oct 01:24
not recorded
lts-v2.10
Pass
12 Oct 00:33
not recorded
lts-v2.12
Pass
11 Oct 23:31
not recorded
lts-v2.14
Pass
11 Oct 22:29
not recorded
master
built integration
Pass
11 Oct 01:21
not recorded
lts-v2.10
Pass
11 Oct 00:33
not recorded
lts-v2.12
Pass
10 Oct 23:30
not recorded
lts-v2.14
Pass
10 Oct 22:33
not recorded
master
built integration
Pass
10 Oct 11:26
fix(psci): allow OS-initiated mode while other cores are off
integration
built refs/changes/26/54926/6
Pass
10 Oct 01:26
not recorded
lts-v2.10
Pass
10 Oct 00:37
not recorded
lts-v2.12
Pass
9 Oct 23:31
not recorded
lts-v2.14
Pass
9 Oct 22:25
not recorded
master
built integration
Pass
9 Oct 21:43
refactor(qti): set up the delay timer from common code
integration
built refs/changes/55/55255/1
Pass
9 Oct 14:59
test: default to PSA APIs
integration
built refs/changes/35/53535/2
Pass
9 Oct 14:04
feat(fvp): scale SP_MIN max size based on SRAM size
lts-v2.10
built refs/changes/48/55248/1
Pass
9 Oct 13:27
fix(build): always define DYN_DISABLE_AUTH
integration
built refs/changes/11/55211/3
Pass
9 Oct 12:03
chore(fvp): bump maximum permitted Trusted SRAM size
lts-v2.10
built refs/changes/32/55232/1
Pass
9 Oct 10:48
fix(lfa): avoid ACTIVATE retry code clash
integration
built refs/changes/29/55229/1
Pass
9 Oct 10:08
refactor(cpus): move C support files into the helpers directory
integration
built refs/changes/27/55227/1
Pass
9 Oct 08:17
refactor(cpus): move C support files into the helpers directory
integration
built refs/changes/27/55227/1
Pass
9 Oct 06:54
not recorded
master
Pass
9 Oct 01:29
not recorded
lts-v2.10
Pass
9 Oct 00:27
not recorded
lts-v2.12
Pass
8 Oct 23:31
not recorded
lts-v2.14
Pass
8 Oct 22:30
not recorded
master
built integration
Pass
8 Oct 21:36
not recorded
master
built integration
Pass
8 Oct 17:24
fix(fvp): absorb BUILD_CPUS_WITH_NO_FVP_MODEL and ENABLE_ERRATA_ALL cores
lts-v2.10
built refs/changes/20/55220/1
Pass
8 Oct 08:46
refactor(cpus): rename Canyon to C2-Ultra
lts-v2.14
built refs/changes/14/55214/2
Pass
8 Oct 08:19
refactor(cpus): rename Canyon to C2-Ultra
lts-v2.14
built refs/changes/14/55214/1
Pass
8 Oct 07:15
fix(fvp): remove GIC crash reporting
integration
built refs/changes/88/55188/2
Pass
8 Oct 06:35
fix(psci): allow OS-initiated mode while other cores are off
integration
built refs/changes/26/54926/4
Pass
8 Oct 01:42
not recorded
lts-v2.10
Pass
8 Oct 00:24
not recorded
lts-v2.12
Pass
7 Oct 23:31
not recorded
lts-v2.14
Pass
7 Oct 22:27
not recorded
master
built integration
Pass
7 Oct 15:08
refactor(lfa): add fallback support
integration
built refs/changes/09/52109/5
Pass
7 Oct 12:42
fix(cpufeat): correctly match the group 3 ID registers space
integration
built refs/changes/37/54137/7
Pass
7 Oct 12:22
refactor(el3-spmc): remove excess overflow checks
integration
built refs/changes/80/55180/2
Pass
7 Oct 10:41
fix(firme): fix attestation unmap error handling
integration
built refs/changes/79/55179/1
Pass
7 Oct 01:37
not recorded
lts-v2.10
Pass

Fleet health

Health checks, not CI results. They never count towards any rate on this page.

0 of 21 health checks failed in the last 7 days.
All passed
Showing the latest 21 checks.
One tick per health check, oldest to newest. Each opens its job.PassedFailedCancelled

Incidents

  1. Lab 17 Sep 2026 to 18 Sep 2026

    LAVA logger DNS failures