Rauru (MT8196)

Status
Live
3 units live.
SoC and family
MT8196, Rauru, Chromebook
Device type
mt8196-rauru-navi
Activity
First seen 14 Jul 2026, last seen 29 Oct 2026.
Data as of 29 Oct 2026, 09:00 UTCLast synced:LAVA 29 Oct 2026, 09:00 UTCJenkins 29 Oct 2026, 09:01 UTCS3 export 7 Oct 2026, 09:53 UTC
Evaluations
179179 attempts, 0 cancelled
Completion
100.0%of 179 attemptsComplete out of complete and incomplete attempts. Cancelled attempts are listed, never counted.
Evaluated pass rate
100.0%of 179 evaluations with a verdictFinal attempts that passed, out of pass and code. Lab 0, cancelled 0 and unclassified 0 are shown, never folded in.
Failed after retries
0 of 1790 failed first time, 0 passed on retry
Changes with a failed boot on this board
0 of 94Allow-CI+2 for TF-A; linked TF-M runs. 0 with no boot verdict. Linked to a change: 59.2% of 179 evaluations

Last 30 days

Evaluations per day, stacked by final outcome.

Test-case detail: 30 Sep 2026 to 30 Sep 2026Test-case detail: 1 Oct 2026 to 29 Oct 2026
Test-case detail: 30 Sep 2026 to 29 Oct 2026. 0 days without data.

History by month

Before the live window we know whether each attempt completed and how retries ended, not why it failed or which change it was. Months with no data held are listed under the chart.

  • Evaluations per month
  • Incomplete attempts, % of attempts
  • Failed after retries, % of evaluations
Incidents marked: Lab 17 Sep.
Test-case detail: September 2026 to October 2026.
Job level only: 1 Oct 2025 to 27 Feb 2026No data held: 28 Feb 2026 to 28 Feb 2026Job level only: 1 Mar 2026 to 6 Sep 2026Test-case detail: 7 Sep 2026 to 30 Sep 2026Test-case detail: 1 Oct 2026 to 29 Oct 2026
Job-level history: 1 Oct 2025 to 6 Sep 2026. Test-case detail: 7 Sep 2026 to 29 Oct 2026. 1 day without data.
  • No data held: 28 Feb 2026 to 28 Feb 2026

Units

CI attempts per physical unit, retries included. Passing on another unit can help identify a unit fault. Health checks are fleet health.

Unit
Attempts
First-attempt failures
Passed on another unit
Passed on the same unit
Last health check
navi-01
57
0
0
0
Complete 28 Oct 10:55
navi-02
52
0
0
0
Complete 28 Oct 10:13
navi-03
70
0
0
0
Complete 29 Oct 04:22

Evaluations

One row per builder build on this board, newest first, with every attempt. CI runs only; 50 of 179 shown.

When
Build
Change
Branch
Attempts
Verdict
13 Oct 11:18
tf-a-builder 2590262
53870/6
test(libc): add memmove unit tests
integration
built refs/changes/70/53870/6
  1. 01
Pass
13 Oct 10:53
tf-a-builder 2589619
not recorded
master
  1. 03
Pass
12 Oct 23:25
tf-a-lts2.14-builder 245912
not recorded
lts-v2.14
  1. 02
Pass
12 Oct 22:23
tf-a-builder 2586538
not recorded
master
built integration
  1. 01
Pass
12 Oct 16:52
tf-a-builder 2585742
55312/1
feat(stm32mp2): save a copy of STM32 header
integration
built refs/changes/12/55312/1
  1. 03
Pass
12 Oct 13:42
tf-a-builder 2584839
55188/3
fix(fvp): remove GIC crash reporting
integration
built refs/changes/88/55188/3
  1. 02
Pass
12 Oct 13:26
tf-a-builder 2583856
not recorded
master
built integration
  1. 01
Pass
12 Oct 13:25
tf-a-builder 2583859
52685/4
fix(plat/qemu): make BDF mapping top inclusive
integration
built refs/changes/85/52685/4
  1. 03
Pass
12 Oct 12:52
tf-a-builder 2582694
not recorded
master
built integration
  1. 03
Pass
12 Oct 11:29
tf-a-builder 2579078
not recorded
master
built integration
  1. 01
Pass
12 Oct 09:54
tf-a-builder 2577671
55227/1
refactor(cpus): move C support files into the helpers directory
integration
built refs/changes/27/55227/1
  1. 02
Pass
12 Oct 07:36
tf-a-builder 2576974
not recorded
master
  1. 03
Pass
11 Oct 23:26
tf-a-lts2.14-builder 245144
not recorded
lts-v2.14
  1. 01
Pass
11 Oct 22:17
tf-a-builder 2575986
not recorded
master
built integration
  1. 03
Pass
10 Oct 23:24
tf-a-lts2.14-builder 244226
not recorded
lts-v2.14
  1. 02
Pass
10 Oct 22:21
tf-a-builder 2575365
not recorded
master
built integration
  1. 02
Pass
10 Oct 11:22
tf-a-builder 2574876
54926/6
fix(psci): allow OS-initiated mode while other cores are off
integration
built refs/changes/26/54926/6
  1. 02
Pass
9 Oct 23:29
tf-a-lts2.14-builder 243677
not recorded
lts-v2.14
  1. 03
Pass
9 Oct 22:22
tf-a-builder 2573505
not recorded
master
built integration
  1. 01
Pass
9 Oct 21:35
tf-a-builder 2572532
55255/1
refactor(qti): set up the delay timer from common code
integration
built refs/changes/55/55255/1
  1. 03
Pass
9 Oct 14:32
tf-a-builder 2571249
53535/2
test: default to PSA APIs
integration
built refs/changes/35/53535/2
  1. 01
Pass
9 Oct 13:25
tf-a-builder 2570519
55211/3
fix(build): always define DYN_DISABLE_AUTH
integration
built refs/changes/11/55211/3
  1. 02
Pass
9 Oct 10:44
tf-a-builder 2569617
55229/1
fix(lfa): avoid ACTIVATE retry code clash
integration
built refs/changes/29/55229/1
  1. 01
Pass
9 Oct 09:51
tf-a-builder 2568596
55227/1
refactor(cpus): move C support files into the helpers directory
integration
built refs/changes/27/55227/1
  1. 01
Pass
9 Oct 08:14
tf-a-builder 2567703
55227/1
refactor(cpus): move C support files into the helpers directory
integration
built refs/changes/27/55227/1
  1. 01
Pass
9 Oct 06:51
tf-a-builder 2566994
not recorded
master
  1. 01
Pass
8 Oct 23:29
tf-a-lts2.14-builder 242858
not recorded
lts-v2.14
  1. 01
Pass
8 Oct 22:26
tf-a-builder 2565340
not recorded
master
built integration
  1. 01
Pass
8 Oct 21:28
tf-a-builder 2564439
not recorded
master
built integration
  1. 03
Pass
8 Oct 08:46
tf-a-lts2.14-builder 242118
55214/2
refactor(cpus): rename Canyon to C2-Ultra
lts-v2.14
built refs/changes/14/55214/2
  1. 01
Pass
8 Oct 08:17
tf-a-lts2.14-builder 241314
55214/1
refactor(cpus): rename Canyon to C2-Ultra
lts-v2.14
built refs/changes/14/55214/1
  1. 02
Pass
8 Oct 07:06
tf-a-builder 2561830
55188/2
fix(fvp): remove GIC crash reporting
integration
built refs/changes/88/55188/2
  1. 01
Pass
8 Oct 06:29
tf-a-builder 2560836
54926/4
fix(psci): allow OS-initiated mode while other cores are off
integration
built refs/changes/26/54926/4
  1. 01
Pass
7 Oct 23:27
tf-a-lts2.14-builder 240556
not recorded
lts-v2.14
  1. 01
Pass
7 Oct 22:33
tf-a-builder 2560355
not recorded
master
built integration
  1. 03
Pass
7 Oct 15:09
tf-a-builder 2559457
52109/5
refactor(lfa): add fallback support
integration
built refs/changes/09/52109/5
  1. 01
Pass
7 Oct 12:35
tf-a-builder 2558469
54137/7
fix(cpufeat): correctly match the group 3 ID registers space
integration
built refs/changes/37/54137/7
  1. 02
Pass
7 Oct 12:11
tf-a-builder 2557928
55180/2
refactor(el3-spmc): remove excess overflow checks
integration
built refs/changes/80/55180/2
  1. 03
Pass
7 Oct 10:41
tf-a-builder 2557300
55179/1
fix(firme): fix attestation unmap error handling
integration
built refs/changes/79/55179/1
  1. 03
Pass
6 Oct 23:25
tf-a-lts2.14-builder 239692
not recorded
lts-v2.14
  1. 03
Pass
6 Oct 22:51
tf-a-builder 2551228
not recorded
master
built integration
  1. 03
Pass
6 Oct 21:12
tf-a-builder 2550434
54926/2
fix(psci): allow OS-initiated mode while other cores are off
integration
built refs/changes/26/54926/2
  1. 02
Pass
6 Oct 20:48
tf-a-builder 2549488
55088/2
fix(psci): run the arch setup before pwr_domain_on_finish()
integration
built refs/changes/88/55088/2
  1. 03
Pass
6 Oct 17:05
tf-a-builder 2547804
not recorded
master
  1. 02
Pass
6 Oct 10:11
tf-a-builder 2547403
54944/2
refactor(cpus): separate helper files from cpu implementations
integration
built refs/changes/44/54944/2
  1. 02
Pass
5 Oct 23:20
tf-a-lts2.14-builder 238671
not recorded
lts-v2.14
  1. 03
Pass
5 Oct 22:13
tf-a-builder 2544549
not recorded
master
built integration
  1. 01
Pass
5 Oct 13:10
tf-a-builder 2544256
55088/1
fix(psci): run the arch setup before pwr_domain_on_finish()
integration
built refs/changes/88/55088/1
  1. 03
Pass
5 Oct 11:31
tf-a-builder 2543243
not recorded
master
  1. 02
Pass
5 Oct 10:46
tf-a-builder 2542535
55087/1
fix(tsp): use VERBOSE instead of INFO
integration
built refs/changes/87/55087/1
  1. 02
Pass
Show the next 50

Fleet health

Health checks, not CI results. They never count towards any rate on this page.

2 of 21 health checks failed in the last 7 days.
2 failed in 7 days, latest passed
Showing the latest 21 checks.
One tick per health check, oldest to newest. Each opens its job.PassedFailedCancelled

Incidents

  1. Lab 17 Sep 2026 to 18 Sep 2026

    LAVA logger DNS failures